Taiwan Semiconductor Manufacturing Company
Layout Sensitivity Model for NTO/CDU APC
2014/5/15 to 2015/5/14
Loading effect is the process result deviation from layout difference. Different layout could have CD , topography , depth or other geometrical difference according to fab mass production experience. By current practice, routine and tedious manual check would be conducted for a new release product at every critical stage to avoid process deviation induced yield loss or device target offset. For example, line bridging due to etch CD bias difference from loading effect, or device target offset due to iso and dense area. With local layout information such as pattern density or line end density as an input to engineer, high risk area and corresponding process stages shall be identified in advance by machine-learning models proposed in this project.